Samsung Announces 'shinebolt' HBM3E Memory.

Samsung held its annual Memory Technology Day in San Jose, and made some important announcements related to memory technology. The highlight of the event was the presentation of the Sheinbolt, Samsung's hpm3e memory, which promises to set new records in memory bandwidth and high-end processor capacity.

chainbolt is designed to offer much higher capabilities and a larger memory bandwidth compared to the HPM 3, which is currently used in high-end processors and HPC-grade. It is based on a new 24 Gbit HP memory template and will be produced on Samsung's advanced 10 nm class node. This technology will be available in both 8-he and 12-he stacks, saving 24 GB and 36 GB of total stack capacity, respectively, 50% more than the HP-3 equivalents (easybolt). Sheinbolt is expected to achieve memory clock speeds of up to 9.8 Gbps / pin, which is 50% faster than the HP 3 products, which may exceed the competition's claims.

These speeds will provide a bandwidth of at least 1 Tb/s and a maximum of 1.225 TB/s for one heap of hpm3e, which significantly exceeds the 819 GB/s data rate of hpm3. This level of performance is critical for high-end processors, especially in the artificial intelligence market, where memory bandwidth and capacity are limiting factors for tasks involving large language models. While Chainbolt is more energy efficient than its predecessor, a significant clock speed improvement may lead to an increase in total power consumption. However, such a power increase is unlikely to deter chipmakers in the high-end processor market, as they are targeting the booming artificial intelligence sector.

Samsung plans to ship the Chainbolt in 2024, with the expectation that it will become available later in the year. Samsung also gave a brief overview of its plans for the hpm4 memory, which is still under development. It is expected that the HP-4 will use advanced technologies of fab and packaging, including vinfit transistors and direct copper-to-copper interconnection, to improve energy efficiency and memory bandwidth. These technologies are necessary to maintain the growth of the HBM memory bandwidth. Samsung expects that the gdr7 memory will be a game changer in terms of memory technology. GDP-7 offers several improvements over GDP-6, such as switching to Pam-3 encoding, enabling 1.5-bit transmission per cycle. This progress results in a 33% increase in bandwidth per pin above GDP 6, with a total bandwidth of 1 Tb/s for a 256-bit memory bus. The gdr7 is also expected to be 20% more energy efficient than the gdr6, thanks to Samsung's 3d1z generation. Notably, GDPR 7 will consume 50% less spare power than GDPR 6 due to additional round-the-clock controls.

The decision to use the Pam 3 encoding for the insidious 7, instead of the more dense PAM 4, is based on slightly lower average error rates and wider margins on the eye window. Samsung expects gddr7 to be adopted by AI chipmakers and even the automotive industry, where non-traditional customers will probably be the first to adopt this technology. Samsung has not yet given a specific date for the mass production of the GDR-7 but expects to be the first seller to ship the next-generation memory, most likely in 2024.

Samsung's advancements in GDDR7 memory are not limited to traditional gaming customers but also extend to AI chip makers and, surprisingly, the automotive industry. Non-traditional customers might be at the forefront of adopting GDDR7, as traditional GPU vendors are still in the midst of their current product generation. While an exact date for mass production of GDDR7 has not been announced by Samsung, the company is poised to lead the market in shipping this next-generation memory, likely hitting the shelves in 2024, ushering in a new era of high-performance memory technology across various industries.