Huawei Claims It Broke von Neumann. I Read the Paper. It Doesn’t Say That.

Cool the Title Down: This Paper Did Not Overturn von Neumann

On September 15, arXiv posted paper number 2609.16787, titled “Nested Parallel von Neumann Architecture and Nested BSP,” with a single author name: Liao Heng. He is a Huawei Fellow, Chief Semiconductor Scientist, and chief architect of Ascend.

Two days later, at Huawei Connect, Huawei announced the Peerium computing architecture, with the promotional line “breakthrough in von Neumann single-machine architecture.”

Treat “breakthrough in von Neumann” with caution. The paper’s title itself says “parallel von Neumann architecture,” placing it inside the von Neumann framework. As long as we still use binary, still use memory, and still have processors fetch and execute instructions, no one escapes von Neumann’s palm. What is being replaced is a more hidden premise: the single machine. The von Neumann setup describes one computer. What AI training needs today is hundreds of thousands of cards working together. Stretching the definition of one computer to a million processors leaves a gap. That gap is what Liao Heng wants to fill.

First, That Uncomfortable Number

Huawei gave a number at the conference: under traditional architecture, the actual model FLOPs utilization (MFU) of a 100,000-card cluster is about 20%. Of the 100,000 cards bought at great expense, most of the time the equivalent of 80,000 are waiting. They wait for data to move, for other cards to finish, for the scheduler to speak.

This is the starting point, far more concrete than talk of a computing-model revolution. Over the past few years, industry discussions about compute have been almost entirely about peak TFLOPS, HBM bandwidth, and process nodes. At the 100,000-card scale, the bottleneck is no longer “computing slowly” but “waiting for a long time.” Peak compute is on paper; MFU is on the bill. Liao Heng’s paper answers a plain question: how to make those 80,000 cards wait a little less.

Nested BSP: An Old Model, Moved Down to the Hardware Layer

Get the ugly truth out first: BSP is not new. Leslie Valiant proposed the model in 1990: a round of computation, a round of communication, a global synchronization, then repeat. MapReduce, Pregel, and later graph computing frameworks all build on this rhythm.

Liao Heng’s novelty lies in two places.

The first is nesting. Traditional parallel models usually have only one layer: either partitioning within a single card or dividing tasks among a bunch of cards. Nested BSP allows parallel structures to be nested layer by layer. Within a card, within a node, within a rack, across racks, across clusters, each layer has its own synchronization granularity and does not drag the others down. This sounds like an organizational chart. Mathematically, it determines where you pause and for how long.

The second, and the one I care about more, is that it intends to put this model into the bus and protocol, rather than stuffing it into a software library. In the past, BSP was something programmers agreed on in code: write to a barrier, everyone stops and waits. Huawei’s approach now is to write synchronization semantics and memory addressing directly into the interconnect protocol, Lingqu. Make “reading a piece of memory across devices” at the hardware level roughly the same as reading local memory. Cross-rack device RTT latency is brought down to 2 microseconds; in traditional architectures this number is on the order of 7 microseconds. Single-hop latency is pressed to 200 nanoseconds, and the UBG switch radix reaches 1024.

These numbers matter because they make “a million cards sharing one address space” go from theoretically feasible to barely sustainable in engineering.

In the past, software pretended to be one machine. Now the attempt is to make the hardware actually behave like one machine.

The Divergence from Nvidia: Where the Boundary Is Drawn

Many articles online treat “peer-to-peer interconnect and decentralization” as a unique Huawei invention. That claim does not hold up. Nvidia’s NVLink plus NVSwitch has long been point-to-point, with no CPU relay and unified addressing between GPUs. GPUs in an NVL72 rack access each other’s memory in a way that is not fundamentally different from accessing local memory.

The difference between the two is more specific and more mundane: where the scale-up boundary is drawn.

Nvidia draws it inside the rack. 72 cards, 144 cards, all high-speed direct-connected, with high density and low latency. The cost is also clear: power walls, cooling walls, and HBM capacity walls press in together. Chip area grows larger, compute units grow quadratically, but power pins and signal pins can only grow linearly along four sides. The I/O wall arrives before the compute wall. This architecture can go another generation or two, but it will become increasingly strained.

Huawei draws it across the entire data center, even across data centers. It does not pursue full interconnect within a single rack; it spreads cards out with optical interconnect, and logically it is still one supernode. The Atlas 950 supernode is planned for a maximum of 8,192 cards, and SuperCluster reaches the 500,000-card level. Atlas 960 uses 5,500 self-developed Hi-ONE optical engines to replace 48,000 800G optical modules, saving 550 kilowatts of power and achieving 99.8% availability.

Trading latency for scale, trading space for process. Which is more advanced is not a useful question. The two companies hold different cards.

Nvidia can get the most advanced process and HBM capacity, so it naturally pursues density. Huawei is choked on process and HBM, so it can only look for margin at the system level. The “18-layer pagoda” Liao Heng proposed in an interview, plus the time-scaling logic of “Tao’s Law” Huawei released this year, are saying the same thing: when the cost-effectiveness of single-layer optimization falls, you can only squeeze efficiency back through cross-layer coordination.

This path also has a practical benefit: the optical communications supply chain is complete in China, and the cost of power and data center infrastructure is low. Trading space for process happens to land on China’s endowments.

A Few Reservations I Still Hold

Time to pour some cold water, the fairly hard kind.

First, the most piercing point: one arXiv paper does not equal a usable system. Single author, no peer review, no open-source implementation, no benchmark tests. At present it is an architectural manifesto, not an engineering acceptance report. Historically, most such manifestos do not survive three years.

Second, “unified memory addressing” at the million-card scale is a hell-level problem. Unified address space is easy; consistency is hard. Consistency can barely be done; the failure domain is what is deadly. In 500,000 cards, a few failing every day is normal. If one node goes down, global synchronization can collapse with it. Hierarchical backup fault tolerance sounds light, but doing it is another matter. Huawei says 99.8% availability, but that is a number under a specific configuration, not a promise for a million cards.

The MFU 20% comparison number is also given by Huawei itself. I have not seen a third-party, same-caliber, reproducible comparison. The full configuration specs of Atlas 950 still have no mass-production measured data, nor any independent third-party evaluation. Comparisons like “card scale is 56.8 times that of NVL144” use each side’s maximum theoretical configuration, which does not equal the load that can actually run.

Last: the ecosystem is the moat, and this paper basically does not touch it. CUDA’s barrier is not single-card performance; it is the operator libraries, debugging tools, migration paths, and developer habits accumulated over twenty years. Although the Lingqu protocol has opened its specification, whether an open protocol can attract heterogeneous vendors, or ultimately becomes “Huawei’s internal standard under a different name,” depends on whether anyone is willing to put money into it. This will only be clear in five years.

So How Should It Be Viewed?

It deserves attention for one reason. Not because of the narrative that “China has finally broken through Western containment.” Mixing that into technical discussion makes it easy to lose sight of things. Nor because the parameters are beautiful. It is because this is a Chinese engineer setting the question at the level of computing models, rather than answering someone else’s question a little better.

Over the past twenty years, the main move of domestic compute has been catching up. Others define instruction sets, we implement; others define interconnect standards, we make compatible; others set “single-card TFLOPS” as the objective function, and we desperately try to match it.

This time is different. Liao Heng changed the objective function, from “single-card peak” to “ten-thousand-card usable MFU.” Then, following this new objective function, he went back to redo chip architecture, bus protocol, cluster topology, and software stack.

Changing the objective function is ten times harder than changing parameters, and ten times slower. It means you have to bear the risk of “possibly choosing wrong,” and you have to wait many years to know whether you were right.

Liao Heng entered Tsinghua’s youth class at 14, spent nearly twenty years doing chips at PMC-Sierra, joined Huawei in 2016, and built Ascend from scratch. In July this year, in an interview, he commented on DeepSeek’s Liang Wenfeng in strong terms: when the whole industry was blindly following the Scaling Law and frantically piling on parameters, Liang Wenfeng actively chose the harder sparse activation architecture. This is no longer algorithm fine-tuning, but a top-level strategic choice running through software and hardware. He said Liang Wenfeng “had already foresightedly gone to solve a problem he anticipated — this is the value of a priorist.”

Algorithmic innovation can widen the road before hardware hits the wall. That this comes from a chip architect’s mouth itself says a lot. He understands that the single-point hardware path has reached its end.

Whether Peerium can succeed, I do not know. Whether Nvidia will follow a similar line of thinking, I also do not know. But one thing is certain: after the last bit of Moore’s Law’s warmth dissipates, everyone will be forced back to the same question: when transistors are no longer free to get cheaper, how should we reorganize computing?